{"id":13096,"date":"2025-08-05T09:54:18","date_gmt":"2025-08-05T09:54:18","guid":{"rendered":"https:\/\/incose.nl\/incose-nl-workshop-2025\/mathworks-1\/"},"modified":"2025-09-23T13:54:01","modified_gmt":"2025-09-23T13:54:01","slug":"mathworks-1","status":"publish","type":"page","link":"https:\/\/incose.nl\/en\/incose-nl-workshop-2025\/mathworks-1\/","title":{"rendered":"Mathworks 1"},"content":{"rendered":"
\"INCOSE-NL<\/a><\/div><\/div><\/div><\/div><\/div><\/section>
\"Stephan<\/a><\/div>

Stephan van Beek<\/h2>\n<\/div><\/div>

Consulting Application Engineer MBSE<\/em><\/p>\n<\/div><\/div>

<\/div><\/div><\/div>

System-on-Chip Meets Systems Engineering \u2013 integrating approaches<\/h2>\n

10:30 – 12:00<\/p>\n<\/div><\/div>

<\/div>

Abstract
\n<\/strong>The growing complexity of modern systems demands advanced hardware solutions, with Field Programmable Gate Arrays (FPGAs) and System-on-Chip (SoC) architectures playing a pivotal role. However, the intricate nature of FPGA\/SoC development requires structured engineering methodologies to ensure reliability, performance, and resilience\u2014especially in demanding environments.<\/p>\n

Leveraging Systems Engineering for FPGA\/SoC Development<\/span>
\nTo tackle these challenges, systems engineering principles are essential for:<\/p>\n

    \n
  • Managing complexity\u00a0by structuring FPGA\/SoC designs with comprehensive requirements models.<\/li>\n
  • Optimizing functional\u00a0allocation\u00a0through effective partitioning techniques for heterogenous architectures.<\/li>\n
  • Enhancing validation & verification\u00a0by integrating fault injection for functional correctness and sensor fault impact analysis.<\/li>\n
  • Accelerating deployment\u00a0and minimizing development time.<\/li>\n<\/ul>\n

    The Road Ahead: SysML v2 and the Future of FPGA\/SoC Development<\/span>
    \nAs FPGAs and SoCs drive next-generation computing, MBSE is evolving to unlock new levels of automation, collaboration, and interoperability. SysML v2 represents a major leap forward enabling integration between various engineering disciplines to realize complex systems with relevant information throughout the system\u2019s lifecycle. The emergence of the SysML v2 API supports this integration by allowing various engineering tools to access a SysML v2 system model.<\/p>\n

    Bio Stephan van Beek
    \n<\/strong>Stephan van Beek is a seasoned technical specialist with over 17 years at MathWorks, Eindhoven, where he helps engineers and organizations across Europe implement Model-Based Systems Engineering (MBSE) and Model-Based Design (MBD) for FPGA and SoC development. With deep expertise in Systems Engineering and Embedded Systems, he guides customers in optimizing design workflows, accelerating innovation, and bridging the gap between algorithm development and hardware implementation.
    \nBefore joining MathWorks, Stephan was part of the electronic design methodology team at Oc\u00e9-Nederland, refining and improving design processes. His career also includes time at Anorad Europe BV, where he specialized in motion control systems. Stephan holds a B.Sc. in Electrical Engineering from the Eindhoven University of Applied Sciences and is passionate about driving efficiency and excellence in engineering design processes.<\/p>\n<\/div><\/div>

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